Altera company signed an agreement with TSMC on FPGA-release matrices using 16-nm process technology. It should be recalled that a year ago, Altera has concluded a similar agreement with Intel, only applied to 14-nm process.
Fresh press release, Intel reported that it extends contract with Altera service multichip packaging chips. In a 14-nm process technology with Tri-Gate transistors matrix generation Stratix FPGA 10 and SoC Altera will be issued in the form of multichip SiP-packaging. The company note that we are talking about packaging System-in-a-Package, and not about the newfangled 2,5 D and 3D. We explain that the package 2,5 D implies partially horizontal arrangement of crystals, using TSVs-connections for mounting crystals on a common substrate, and 3D-packing - a vertical stack of crystals with through TSVs-compounds. In the case of SiP it also comes as a rule, placing the stack of crystals, but only with external wired strapping (see picture above).
According to Intel, use SiP economical than 2,5 D-and 3D-packaging. At the same time the company has more than 10 years of experience in manufacturing processors XScale, which in addition to the computational core carried chip flash memory and a single crystal of SRAM. For Altera, Intel will be packaged in a single housing FPGA-matrix, DRAM, SRAM, ASIC, processor, analog components and much more. Just as importantly, the company has its own facilities for packaging and testing, which makes it a unique contract manufacturer. TSMC Company, for example, although it is able to produce 2,5 D-combination, packaging and testing orders from contractors.
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