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JEDEC talked about DDR4 memory specification


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JEDEC talked about DDR4 memory specification


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POSTER: computer news   ||   JEDEC TALKED ABOUT DDR4 MEMORY SPECIFICATION

DATE:2011-08-24

The specifications for memory modules and other microelectronics developed and approved by JEDEC - standardization body semiconductor electronics industry Alliance (Electronic Industries Alliance, EIA).  EIA has about 300 members who participate in standards development, serving the needs of industry.  JEDEC published the key attributes of the forthcoming RAM DDR4 standard.  Final specifications will be ready by mid-2012.  Modules are executed in accordance with the new specifications will  not only improve performance but will consume less energy.

The main update is energy efficiency,.  First, the reduced supply voltage to 1.2 volts.  Second, the architecture will be used by groups of banks, with independent signal lines.  Thus, each group of banks will be able to work independently, allowing you to disable the idle group.  It is not difficult to guess that the new architecture will have a positive impact on energy consumption modules.

Minimum data rate for each line was 1.6 gigahz per second, however, the standard in the future implies a doubling of capacity (ie, the effective memory speed will be 1600-3200 MHz).  If we compare this figure with DDR3, then the standard for the current generation is at 1.6 GT / s (1600 MHz), but in practice, producers managed to exceed the limit.  D

Among other improvements we note the following:

  • POD12 (Pseudo Open Drain) conformance - rated voltage was 1.2 volts, reducing power consumption in modes of reading and writing;
  • New data bus CRC - will be able to detect transmission errors on the data bus, even for units without a block ECC;
  • support data masking;
  • pseudo-interface flow on the bus DQ;
  • internal voltage generation and maintenance of stability VrefDQ bus DQ even with drops in voltage VDD over time;
  • support new algorithms verify the address and command bus;
  • support mechanism for DBI, which is responsible for energy efficiency, and integrity of data being written.

Another important feature is the use of memory controller interface, point to point.  This means that each channel can connect only one module DDR4, which means that in the future, manufacturers will have to significantly increase the volume of produced modules.  Commercial introduction of new memory standard is not expected until 2013.  Analysts predict that by 2014, DDR4 will be used only in 12% of computer systems around the world.  At the moment, the release of experimental  2GB modules engage Samsung and Hynix.


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JEDEC talked about DDR4 memory specification


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