Europeans presented a promising framework for the 5-nm transistors

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POSTER: computer news   ||    EUROPEANS PRESENTED A PROMISING FRAMEWORK FOR THE 5-NM TRANSISTORS	DATE:2016-12-10
In The conference IEEE International Electron Devices Meeting 2016 (IEDM) in San Francisco, the representatives of the European research center CEA-Leti (Grenoble, France) presented two interesting document: NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs and Vertically Stacked-Nanowires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source / Drain .  The first document describes a theoretical model of  transistor with a stack structure and encompassing  gate, and the second is about the practical implementation of the 5-nm transistor stack structure with silicon nanowires and silicon-germanium gate (pictured below). In the first paper, researchers presented and proved the validity of methods of calculation of the surface potential inclusive gate (Gate-All-Around, GAA), taking into account many factors, including negative quantum effects, as well as taking into account the round, square and rectangular configurations gate FinFET transistors and conventional planar transistors .  The model also includes calculations of the transitional structures using nanowires and nanosheets (NanoWire / NanoSheet, NW / NS). For the proof of the model and the possibility to produce transistors with nanowires with the norms of 5 nm or less, researchers have created a stack of the transistor structure with built-in splitter.  Separator in practice shown to be effective in reducing spurious interference from adjacent gates.  Moreover, in practice the shutter implemented manufacturing technology of silicon and germanium.  This technology is sure developers can replace the current manufacturing process technology with transistors and metal gate insulator with high dielectric constant (HKMG). Related Products :

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