The conference PCI-SIG Developers Conference 2017 was held last week. VIP-SIG responsible for the development of the PCI Express interface reported on the completion of the development of two versions of the standard: PCI Express 4.0 version 0.9 and PCI Express 5.0 version 0.3. The first one is close to the final version and will be considered until July 3, after which a decision will be made on further actions, and the basic draft PCI Express 5.0 version 0.3 will be reviewed by August 7.
The development of the PCI Express 4.0 standard took about seven years. Compared to the previous version, the transmission rate on one line will be doubled from 8 Gbit / s to 16 Gb / s. The transmission speed of one line in the version of PCI Express 5.0 will also double - up to 32 Gb / s. The development of PCI Express 5.0, which is indicative, is only two years. The organization PCI-SIG promises to present the final specifications of the next version of the standard as early as 2019.
Support for PCI Express 4.0 is already implemented in the architecture of IBM Power9 processors. The commercial assembly of systems with these processors should begin this year. Developers of physical layer solutions, Cadence, PLDA and Synopsys are ready to provide interested manufacturers with solutions for the release of controllers supporting PCI Express 4.0. So, the controller (bridge between PCIe-periphery and Ethernet) is prepared by NEC. It is interesting to add that the PCI
Express 4.0 bus will be actively used in automotive electronics.
As for the prospective PCI Express 5.0 bus, it is necessary in the light of the popularization of solutions for machine learning and for artificial intelligence systems. Also, the PCI Express 5.0 bus will provide high-speed exchange through network controllers, and also will need different kinds of accelerators. Related Products :
|